AMD Zen 7 'Florence' leak teases 288-core Epyc chips and major laptop efficiency gains
AMD's next-generation server platform could push mainstream core counts into territory that was unthinkable just a few years ago, with workstation and high-end desktop users potentially set to benefit from the same building blocks.
According to a set of slides shared by known hardware leaker Tom, the host of Moore's Law Is Dead on YouTube, AMD's Zen 7 EPYC flagship, codenamed Florence, relies on two "Dwarka" I/O dies and two "Mathura" memory dies, both named after ancient Indian cities of considerable historical and spiritual importance, paired with up to eight 36-core Steamboat CCDs, yielding 288 cores per socket.
Each Steamboat CCD combines a Zen 7 core die on TSMC's A14 node with a separate L3 cache chiplet on N4P, stacked underneath rather than on top as with the existing 3D V-Cache. The slides list 7 MB of L3 per core, a PCIe 6 + CXL 3.2 interface, xGMI4-80G link speed, and a TDP of up to 600 W.
Both the Dwarka IO die and the Mathura memory die are indicated to use TSMC's N3C process. One slide shows an A0 tape-out scheduled for October 2026, with production targeted for mid-2028 and a launch around the end of that year. A separate roadmap entry points to a PCIe Gen 7 platform arriving around 2029, possibly as a mid-generation refresh on a new socket.
Buyers of current-generation AMD platforms may not have to swap sockets to benefit from the next architectural leap, and laptop users in particular stand to see some of the biggest gains. The leaked documents indicate that Zen 7 CCDs are backwards compatible with previous-generation Kedar and Weisshorn IO dies, while Silverton CCDs will work with Badri, Kedar, Puri, and Dwarka IODs across SP7 and SP8 packaging, with support for 2, 4, 6, or 8 CCDs per socket. Threadripper and HEDT support via the Dwarka IOD is explicitly called out.
A separate performance table for the consumer-oriented Silverton and Silverking chiplets lists per-core gains of 16 to 20 percent at sub-9 W server workloads, and 30 to 36 percent in 3 W/core client APU scenarios, pointing to particularly strong efficiency improvements for thin-and-light laptops.
Tom speculates that the 36-core Steamboat CCD's similar width to the 16-core Silverton could theoretically allow AMD to fit two Steamboats on AM5 for a 72-core desktop chip, though no leaked slide confirms such a product. The leaker himself suggests any such part would more likely target embedded customers than the DIY market.
Do watch his video, linked below, for a detailed look at the leaked information and his take on it.
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