There has been plenty of news about Intel's Xe architecture lately, with the DG1 appearing on 3DMark, Sisoft Sandra and Geekbench since February. However, it turns out that Intel published information about its Xe architecture in January, but no one noticed.
Hidden within the Intel® Iris® Plus Graphics and UHD Graphics Open Source Programmer's Reference Manual are references to "Gen12 HP". We already know that Gen12 means the Xe architecture, with HP indicating a "High Performance" GPU. Intel has already confirmed that it is targetting Xe-HP for workstations and high-end graphics.
Brought to our attention by @KOMACHI_ENSAKA and Hardwareluxx, the Programmer's Reference Manual includes the phrase "new systolic pipeline addition on EU from Gen12 HP onwards". According to Hardwareluxx, this means the volume of execution units (EUs) on which Gen12 HP GPUs and the Xe-HP architecture are based.
Test drivers have indicated that Gen12 HP DG2 GPUs will offer 128, 256 and 512 EUs. Wccftech opines that this should translate to up to 10-15 TFLOPs of FP32 Compute output based on information about the DG1.
Intel is also expected to release the Xe-HPC architecture too, which it is is targeting for exascale and Cloud GFX computing. The company detailed its strategy for the Xe-HPC architecture in December.
Source(s)
Intel via @KOMACHI_ENSAKA, Hardwareluxx & Wccftech