First Intel 7 nm wonder comes to life, Raja Koduri reveals full die shot of the Ponte Vecchio Xe HPC 2-tile GPU with 8,192 cores
Intel's Raja Koduri recently tweeted a photo of a 2-tile Ponte Vecchio Xe HPC die claiming that it includes seven advanced silicon technologies and called it a "thing of beauty". This Xe HPC GPU offers 16 clusters with 64 execution units (EUs) each for a total of 1,024 EUs i.e. 8,192 cores.
While Raja didn't exactly detail which seven advanced silicon technologies he was alluding to, Wccftech managed to get annotations for this die that offer more insights. Wccftech claims that it has verified this annotation from at least two of its sources. According to the publication, the seven advanced silicon technologies could likely be:
- Intel 7 nm process
- TSMC 7 nm process
- Foveros 3D packaging
- Embedded multi-die interconnect bridge (EMIB)
- Intel 10 nm Enhanced SuperFin process
- Rambo Cache
- HBM2 VRAM
On the top left and bottom right corners we have the Xe Link I/O tile fabbed on the TSMC 7 nm process. We also see two pairs of differently sized HBM2 dies on either side of the compute tiles. The compute units are fabbed on Intel's own 7 nm process, which means we are seeing Intel's new process technology for the first time in the wild.
Running in the middle of each of the 8-compute unit clusters is what appears to be the Rambo Cache fabbed on Intel's 10 nm Enhanced SuperFin process. Surrounding each of the clusters on three sides are passive die stiffeners that do not contain any logic.
Wccftech notes that beneath the tiles is a 10 nm base die while the EMIB interconnect is beneath the passive die stiffeners and the HBM2 memory. The whole package uses Intel's Foveros 3D packaging technology, so there's a lot more complexity to it than meets the eye.
Raja said that this particular package is now ready for power-on. Ponte Vecchio will launch some time in late 2021 or early 2022 and is primarily aimed at datacenter and HPC applications such as the Aurora exascale supercomputer.