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AMD's EPYC Rome CPUs could have double the PCIe lanes of the corresponding Intel chipset

STH's proposed PCIe arrangement for a dual-socket Rome CPU. (Source: ServertheHome)
STH's proposed PCIe arrangement for a dual-socket Rome CPU. (Source: ServertheHome)
A blog called ServertheHome has drawn on the latest leaks and info on EPYC Rome to conclude that it could have between 128 and 160 PCIe lanes. By contrast, the competing Intel Xeon Platinum 9200 solution may have only 80. On top of that, the Xeon's lanes may be Gen3, whereas Rome is likely to have Gen4.

EPYC Rome is the latest generation of AMD's server-grade CPUs. They are projected to be serious competition for the Intel competitors in this market, not least because a partnership with Google revolving around this new silicon is currently under consideration by the company. Now, a new blog post also alleges that Rome can do far better than its big blue counterpart in terms of an important spec: PCIe lane counts.

It is known by now that a single-socket Rome CPU is likely to support 128 Gen 4 lanes. However, these chipsets may also be scaled up to dual-socket solutions. In this case, ServertheHome has hypothesized that such a processor could support up to 160 lanes. This is based on observations that a dual-socket Rome could have up to 16 (i.e. 2x8) PCIe links. In that case, up to 5 of these per socket could be used by the CPU, leaving 3 each to link the sockets themselves.

This translates to a maximum of 160 lanes, or twice as many as the Xeon Platinum 9200. However, obviously, the CPU/socket-link ratio could be 1:1, leaving the maximum dual-socket Rome PCIe count at about 128. However, this slightly less astronomic number would still be bad news for Intel, as the 9200 is said to only support Gen3 lanes. However, the real-world server perfornance of the future will be the better test of AMD vs. Intel in 2019 and beyond.

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> Notebook / Laptop Reviews and News > News > News Archive > Newsarchive 2019 04 > AMD's EPYC Rome CPUs could have double the PCIe lanes of the corresponding Intel chipset
Deirdre O Donnell, 2019-04- 7 (Update: 2019-04- 7)