For the original German article, see here.
Bristol Ridge and Stoney Ridge were announced during Computex on June 1, 2016 and are already shipped in the A-series APUs starting in June. Bristol Ridge is the designation for the more powerful and expensive APUs and direct successor to Carrizo. They are manufactured in a quad-core die (2 modules) with 250.4 mm² and 3.1 billion transistors.
Stoney Ridge is the designation for the smaller and cheaper entry-level APUs and is the successor to Carrizo-L, which is based on a completely different architecture compared to Carrizo (e. g. even more frugal Puma cores instead of Excavator). It uses a dual-core die (1 module) with 124.5 mm² and 1.2 billion transistors.
Both dies are still based on the same architecture and offer the same features. The technical specifications are similar to Carrizo:
One new feature is the DDR4 (LP) support of the 128-bit memory controller, which was reserved for some embedded processors so far and not activated for Carrizo.
More details about Carrizo, the similar Excavator CPU cores and the GCN GPU cores are available in our Carrizo launch article.
Bristol Ridge is still manufactured in a 28 nm process at Global Foundries, but the recipe was improved. This means AMD did not have to redesign the whole chip and was able to use existing templates. Still, there are noticeable improvements: Bristol Ridge can now use higher clocks at the same consumption (or the other way around, respectively). The picture on the right illustrates the improvements from Carrizo (red) to Bristol Ridge (green). The mobile APUs consumption of between 15-35 Watts is usually in the area of 1/2-2/3 of the curve (roughly). Bristol Ridge's efficiency increases of about 50% are supposed to be a result of the improved process.
AMD advertises the following four new features for Bristol Ridge and Stoney Ridge, respectively, compared to Carrizo.
In addition to the 8 different Power States the operating system can use to control the APU, there are now two so-called Shadow P-States. Thanks to measurement electronics and 500 sensors inside the silicone, these two P-States allow for a more precise control.
Thanks to an improved prognosis for long-term reliability, AMD can use much higher Boost clocks. This means the APU can run closer to the limit of its environment without jeopardizing the long-term reliability of the chip. This feature accounts for up to 12% of the performance gains according to AMD, because they do not have to rely on conservative estimates.
This feature is only available when the notebook manufacturer configures the device together with AMD. It requires sensors underneath the palm rest and at the bottom of the notebook, for instance. In combination with corresponding calculations about heat distribution inside the notebook, the Boost duration can be increased compared to internal sensors from the processor. This should result in noticeably higher performance for short workloads (web browsing, office, etc.) in particular.
The selection process for processors usually includes the tolerances of voltage regulators and the aging of transistors over the lifetime. Because of this and the differences during binning (selection of processors) and the final notebook, the clocks can only be chosen conservatively. With the BTC technology, the voltage is measured every time the device boots up and the results are compared with the initial boot sequence. This means you can compensate for tolerances and aging processes and select more aggressive voltages.
Thanks to the previously mentioned methods, AMD partially manages significant performance and efficiency improvements depending on the TDP category compared to Carrizo. Depending on the model, the Boost clocks for the CPU and GPU should be maintained for longer periods. Another factor is the higher specified clocks for many models with the same TDP range. Because of this, the performance of all models should be higher. The IPS performances of the processor and graphics cores on the other hand did not change.
Thanks to 9 more months of validating and testing (in addition to the 12 months for Carrizo), AMD was able to activate additional features in the silicone and therefore improve the efficiency. The manufacturer also switched to an improved 28 nm process, which brings additional performance gains. This two-stage launch of Carrizo and Bristol Ridge was planned from the beginning according to AMD. These improvements also result in the discontinued Carrizo-L, which is replaced by a one-module die (dual-core) from the Bristol Ridge architecture called Stoney Ridge.
