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Teardown shows Huawei Kirin 9050 Pro uses a 3D V-Cache-like stacked design for the SoC, and the results are impressive

The Huawei Mate 90 Pro Max, featuring Huawei's latest chip, the Kirin 9050 Pro
ⓘ Huawei
The Huawei Mate 90 Pro Max, featuring Huawei's latest chip, the Kirin 9050 Pro
Geekerwan's teardown and analysis of the Kirin 9050 Pro show how Huawei's first LogicFolding chip works, and the results are impressive.

Geekerwan has published a teardown of the Huawei Kirin 9050 Pro, the SoC in the Mate 90 Pro Max. The channel had a lab slice the chip open and rebuilt its internals in 3D to show how Huawei's first LogicFolding chip works.

Two dies, bonded together

A conventional SoC has a substrate, metal layers and one logic layer on top. The Kirin 9050 Pro instead has two dies stacked and joined by copper-to-copper hybrid bonding, which links their metal layers. The compute die is made on SMIC N+3 (roughly a notch better than 6 nm-class nodes from other foundries). The secondary die, which holds the cache, I/O interfaces and PLLs, is made on SMIC N+2 (roughly equal to TSMC N6). Neither Huawei nor SMIC has confirmed the nodes directly.

Power and signals reach both dies through through-silicon vias (TSVs). Geekerwan counts about 80,000 of them connecting the chip to the substrate. They pass through the lower die to reach the upper die, and their keep-out zones consume about 8% of the bottom die's usable area.

The concept is similar to AMD's 3D V-Cache, with cache on a separate bonded die. Here the hybrid bond connections are much denser, which should shorten the path between execution units and cache and reduce latency.

Huawei's LogicFolding does not simply place whole blocks on one die or the other. Each major block spans both dies, which can be seen in Kurnal's die shot. In the prime core, most execution units sit on the top die, while the L1 and L2 caches sit on the bottom die directly beneath the load/store units. The same applies to the GPU, ISP, NPU and modem. The shorter interconnects should cut latency and allow lower voltage at the same clock speed. Cache, I/O interfaces and PLLs go on the bottom die because they run cooler and are less process-sensitive. Compute blocks go on the top die, where heat dissipation is better.

Revamped NPU

The NPU is the biggest upgrade. Its combined area across both dies is 150% larger than the 9030 Pro's. Geekerwan measured 68 TOPS of INT8 throughput and a threefold prefill improvement with a 3B-parameter model.

Phones with the chip support an on-device 30B-A2B mixture-of-experts model (30B parameters, 2B active at a time). It handles offline photo organization and edit suggestions and powers Huawei's AI assistant, paired with a 6B multimodal model for the edits. For comparison, Apple uses a 20B-A4B on-device model. All Kirin 9050 Pro phones have 16 GB of RAM, so Huawei can keep a larger model in fast memory. The NPU still trails the latest competitors, so Huawei only activates a smaller share of the parameters compared to Apple's solution.

Impressive gaming results

In gaming tests, Geekerwan says the Huawei Mate 90 Pro Max's performance in Genshin Impact beats that of some Snapdragon 8 Elite Gen 5 phones and trails that of phones powered by the Snapdragon 8 Elite Extreme Gen 6 and Apple A19 Pro only slightly. In Wuthering Waves, the chip ranks ahead of Dimensity 9500 phones. In Neverness to Everness, it nearly matches Dimensity 9500 and Snapdragon 8 Elite Android phones, albeit the Android devices run at a slightly higher resolution.

Still, the results depend heavily on games ported for HarmonyOS. Titles run through a translation layer, such as Arknights: Endfield, are less efficient and have lower frame rates.

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> Expert reviews and news on laptops, smartphones and tech innovations > News > News Archive > Newsarchive 2026 10 > Teardown shows Huawei Kirin 9050 Pro uses a 3D V-Cache-like stacked design for the SoC, and the results are impressive
Bùi Giang, 2026-10- 3 (Update: 2026-10- 3)