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New AMD Athlon APUs leaked online with expected base clock rates

The Athlon 200GE and 220GE are dual-core chips. (Image source: AMD)
The Athlon 200GE and 220GE are dual-core chips. (Image source: AMD)
A couple of AMD processors have been revealed online: The Athlon 300GE and the Athlon 320GE. Unfortunately, there are almost no details to accompany the supposed names of the chips apart from the alleged base clock rates. The Athlon 300GE will apparently clock at 3.4 GHz while the Athlon 320GE offers a little more at 3.5 GHz.

Noted leaker Tum Apisak has posted some scant details about a potential chip refresh from AMD. The names for the two APUs that have been revealed would suggest that they are simply updated versions of the Athlon 200GE and Athlon 220GE APUs that were launched in December of last year. Those two processors had clocks of 3.2 GHz and 3.4 GHz, respectively, so the new chips only bring minimal upgrades in terms of base clock rates (boost is unavailable on the 200GE and 220GE APUs).

It’s a little unclear which microarchitecture AMD would use for an Athlon 300GE and Athlon 320GE, though. Zen+ seems the most likely, as the Picasso desktop APUs should be launched soon, and the names of the processors will start leaking out. There has been a mention of Zen 2 here and there, but this seems very unlikely, as it will be the Matisse desktop CPUs that are released first not the APUs.

One interesting point made by HardZone.es is that Vega 9 could be the iGPU that finds its way as part of the Athlon 300GE and Athlon 320GE SoCs. The Raven Ridge desktop APUs mentioned above utilize Vega 3 for the GPU component, and it’s possible AMD may upgrade the graphics solution. The same source also speculates that the red team might even allow boost for these next-generation affordable Athlon APUs, which would please overclockers on a tight budget.

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Source(s)

Twitter (Tum Apisak)

HardZone.es (in Spanish)

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> Notebook / Laptop Reviews and News > News > News Archive > Newsarchive 2019 05 > New AMD Athlon APUs leaked online with expected base clock rates
Daniel R Deakin, 2019-05- 5 (Update: 2019-05- 5)