New details on AMD's hybrid core technology leaked with Ryzen 8000 Strix Point engineering sample: 4x Zen 5 P-cores, 8x Zen 5c E-cores and 24 threads
AMD revealed a few months back that future processors will integrate hybrid cores similar to Intel’s performance and efficiency cores and insider reports released this June suggested that the first models to adopt this approach could be the Ryzen 5 7540U and Ryzen 3 7440U APU combining Zen 4 and Zen 4c cores. There is no official confirmation for such claims, since these models are not yet available, but a new leak focusing on next year’s Ryzen 8000 Strix Point APU featuring Zen 5 cores allegedly offers more proof regarding a hybrid architecture.
The Strix Point leak was posted earlier today on the performancedatabases.com site, which looks quite barebones and only features this entry in the leaks section. There are two watarmarked pictures with CPU-Z and HWiNFO details for what looks like a 4 nm Strix family processor with 45 W TDP.
Both CPU-Z and HWiNFO identified that the upcoming Strix APU is still compatible with the AVX-512 instruction set, so AMD is unlike to drop support any time soon. Intel, on the other hand, is no longer supporting these instructions since late 2022.
Strangely enough, the core clocks of the Strix Point APU are all over the place, with CPU-Z reporting close to 3 GHz, while HWInfo reports 8.8 GHz base and 6.25 GHz boost. Apparently, this is a very early engineering sample that is missing some ID codes.
CPU-Z also identifies four “performance” cores (Zen 5) and 8 “efficiency” cores (Zen 5c). However, AMD’s smaller cores support multithreading and are essentially cut-down versions of the Zen 5 cores, unlike Intel’s E-cores that are limited to a single thread and actually feature an older architecture compared to the P-cores. As such, this is a 12-core / 24-thread sample.
The cache readings seem to be unusual, as both apps report 48 KB for L1 Data and 32 KB for L1 Instructions. Each of the P-cores can access 1 MB of L2 cache, while the E-cores appear to form two groups of 4 cores, each accessing 1 MB of L2 cache. CPU-Z reports 8 MB of L3 cache, whereas HWiNFO reports 16 MB.
AMD is expected to launch the Strix Point and Strix Halo mobile processors next year. Unfortunately, there is no info pointing to the inclusion of the RDNA 3.5 iGPUs for now.