Leaked AMD internal slides show detailed architecture specs, IPC gains and release dates for upcoming Zen5 and Zen6 APUs

Moore’s Law Is Dead has been leaking tidbits on AMD’s upcoming Zen5 and Zen6 architectures since late 2022, but his most recent video is presenting a more clearer picture with updates to the roadmap, specs and IPC gains, claiming that this info comes directly from AMD’s internal presentations. However, the roadmap slide might be a bit outdated, as it does not seem to be particularly clear on release times. MLID estimates that Zen5 (Nirvana) built on 4 nm / 3 nm nodes could launch in early 2024, while Zen6 (Morpheus) built on 3 nm / 2 nm nodes could come in mid/late-2025.

Unlike other leakers who were citing fantastic 30%+ IPC gains for Zen5 (Ryzen 8000 series) over Zen4, MLID’s sources seem to be more realistic and down-to-earth, with IPC increases of ~10-15%+. As for Zen6 (Ryzen 9000), the IPC gains might turn out even lower over Zen5, with at least 10% estimated advantage. This all depends on the actual “achieved” IPC for Zen5, which is not yet shown on the slides and will be known after release.

Furthermore, MLID points out that Zen5 will still feature one I/O die and two-CCD design introduced with Zen2, whereas Zen6 will feature a new design, possibly with stacked CCDs on top of the IOD + ultrafast Silicon Bridges between CCDs. Thus the Zen5 processors will feature a 16 full performance core complex (or up to 32 Zen5c low power core complex), and the Zen6 ones will feature a core complex with as much as 32 cores, so we can expect high-end desktop processors with 16 performance cores per CCD.

When it comes to actual architecture improvements, Zen5 will get a big boost in AVX-centric workloads and at the same time keep way lower TDPs compared to Intel’s figures. Zen6 on the other hand, will also focus on improving the XDNA AI / ML accelerator cores with FP-16 instructions, plus it will add a new gen of Infinity Fabric and a new memory profiler. With the new core design, Zen6 is supposed to achieve “monolithic levels of latency and efficiency” even though it is using interconnected chiplets. Because of the stacked nature of the package, Zen6 might deliver well above 10% IPC gains in some games, yet it might require a jump to a new socket.

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