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Intel shows off a 10nm wafer and a bevy of other developments on the occasion of Technology and Manufacturing Day

Intel's Stacy Smith shows off a 10nm 'Cannon Lake' wafer. (Source: Intel)
Intel's Stacy Smith shows off a 10nm 'Cannon Lake' wafer. (Source: Intel)
At its Technology and Manufacturing Day held in Beijing, Intel showcased a number of new developments ranging from the 10nm process for its upcoming 'Cannon Lake' chips to the first commercially available 64-layer 3D NAND for data centers. The company also shared plans for its first 10nm FPGA codenamed 'Falcon Mesa'.
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Intel celebrated its Technology and Manufacturing Day in Beijing, China, yesterday and used the occasion to deliver key updates on its developmental roadmap. Intel's group president of Manufacturing, Operations and Sales, Stacy Smith, re-iterated that Intel's manufacturing process is advancing in accordance with Moore's Law and that Moore's Law is not ending anytime soon. For those not in the know, Moore's Law was first propounded by Intel co-founder Gordon Moore in 1965. It states that the number of transistors and resistors on an integrated circuit doubles approximately every two years. The current doubling rate is approximately 18 months. Mr. Smith said Intel has a three-year lead in process technology and is the main driver of Moore's Law. 

Intel Senior Fellow, Mark Bohr presented the salient features of the 10nm process. Intel's 10nm process has currently the world's tightest transistor and metal pitches, with over 100 million transistors per mm2. Just like the current 14nm process, the 10nm family will sport a triplet of 10nm, 10nm+, and 10nm++ processes. The 10nm 'Cannon Lake' wafer was displayed during the presentation for the first time. The new 10nm process will also power the demands of enterprises and data centers. Upcoming field-programmable gate arrays (FPGAs, codenamed 'Falcon Mesa') will employ the 10nm++ process and are poised to power data centers, wireless 5G, network function virtualization (NFV), and many industrial applications. ARM SoC will soon be developed using Intel's 10nm process with performance north of the 3GHz mark. Intel showed off a 10nm wafer containing ARM Cortex A-75 cores. 

Finally, Intel said that it will be shipping the first 64-layer triple level cell (TLC) 3D NAND SSD targeted towards datacenters. Top-tier cloud service providers have already been testing the new TLC 3D NAND SSDs since August this year and Intel will soon make the product available for data centers by year end. 

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Vaidyanathan Subramaniam
Vaidyanathan Subramaniam - Managing Editor - 1355 articles published on Notebookcheck since 2012
Though a cell and molecular biologist by training, I have been drawn towards computers from a very young age ever since I got my first PC in 1998. My passion for technology grew quite exponentially with the times, and it has been an incredible experience from being a much solicited source for tech advice and troubleshooting among family and friends to joining Notebookcheck in 2017 as a professional tech journalist. Now, I am a Lead Editor at Notebookcheck covering news and reviews encompassing a wide gamut of the technology landscape for Indian and global audiences. When I am not hunting for the next big story or taking complex measurements for reviews, you can find me unwinding to a nice read, listening to some soulful music, or trying out a new game.
contact me via: @Geeky_Vaidy
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> Notebook / Laptop Reviews and News > News > News Archive > Newsarchive 2017 09 > Intel shows off a 10nm wafer and a bevy of other developments on the occasion of Technology and Manufacturing Day
Vaidyanathan Subramaniam, 2017-09-20 (Update: 2017-09-20)