Intel's next gen Atom CPUs may integrate L3 cache memory
The ultra low-voltage Atom family of CPUs from Intel is scheduled to get a substantial upgrade later this year with the release of the Lakefield and Snow Ridge 5G-ready models. Intel already announced that the new Lakefield chips will feature the Foveros hybrid design that combines a desktop-grade Sunny Cove core with four Tremont ULV cores. Intel also recently updated the documentation for the upcoming Atom family, and it looks like there is a fair chance that the upgraded chips will integrate L3 cache memory.
This would be the first time Intel introduces L3 cache to ULV chips. There are not many details on the exact implementation, but the L3 cache is most likely going to be featured by the desktop-grade core part of the hybrid design. The possible L3 cache inclusion was spotted on Intel’s 01.org site that mentions Snow Ridge chips tested for L3 cache hit/misses.
An L3 cache inclusion would certainly provide a performance boost, but it would also mean that the new Atom chips are getting a TDP bump. Of course, this bump has to be minimal in order to keep the voltages as low as possible, so the new Foveros-based 3D packaging has to take this into account. Since the L3 cache could be featured only on the desktop-grade core part, it is yet unclear if Intel will extend the L3 cache to be shared between the desktop-grade and the ULV cores.
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