Intel previews the Foveros 3D packaging technology in upcoming Lakefield hybrid CPUs
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We know that Intel is developing a 3D stacking technology called Foveros that enables stacking heterogeneous chips on top of each other as 'chiplets'. Intel showed off Lakefield CPUs using Foveros at CES 2019 and now is previewing the hybrid CPU in a bit more detail.
The first Lakefield CPUs will use five physical CPUs configured something on the lines of ARM's big.LITTLE setup — a larger 10 nm CPU based on the Sunny Cove architecture with four 10 nm smaller cores. Apart from the five CPU cores, we also see an LP-DDR4 memory controller, 1.5 MB L2 cache, 0.5 MB medium level cache, and a 4 MB last level cache (L3 cache). We also see the integrated Gen11 GPU with 64 EUs along with a dedicated image processing unit for cameras along with a JTAG for interfacing with the rest of the motherboard components all in a package area of 12x12 mm.
The above components are part of what Intel calls the Compute Chiplet with CPU and GPU. On top of the compute chiplet are two DRAM layers and below the compute chiplet is the base die with cache and I/O. Intel says the combined SoC should enable longer battery life, improved performance, and enhanced connectivity and can be implemented in boards that are just 30x125 mm, or in other words, about the length of a ballpoint pen.
Intel expects Lakefield to offer new and innovative form factors that are thinner, lighter, and more powerful including dual-screen and foldable devices. Lakefield surely seems promising can open up more ways of integrating custom IP as chiplets on the same SoC.
Check out Intel's video below and let us know what you think of the new Foveros packaging technology.
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