Ventana and Imagination Technologies develop RISC-V CPU-GPU that may outperform AMD's EPYC Bergamo 128-core CPU

Ever since Nvidia tried to acquire Arm, giving considerable pause to the entire computing industry in regards to the future of Arm’s CPU core architecture, RISC-V has been seeing increased support backed by rapid performance gains that now make it a real alternative to Arm and even to x86. While the CPU side seems to be fully covered by the RISC-V architecture for the moment, the GPU side is somewhat lacking. As a more prominent RISC-V processor maker, Ventana is now planning to bring extensive GPU support through a collaboration with Imagination Technologies. The two companies aim to deliver a fully scalable CPU-GPU with all the latest RISC-V features from the RVA23 update.

Ventana’s new RISC-V CPU-GPU chiplet will scale up to 192 cores and will be aimed at a wide array of applications, from automotive and edge or IoT computing to data center, AI/ML and high-performance. An emulation module for the GPU side working in tandem with the upcoming Ventana Veyron V2 processor is expected to be showcased next week at the RISC-V Summit.

The RISC-V GPU developed by Imagination Technologies may act as a regular graphics accelerator, but, when paired with many RISC-V CPU cores for HPC use, the chip will essentially become a GPGPU unleashing its full parallel processor acceleration. This can vastly improve the performance of the upcoming Veyron V2. Ventana is estimating that the V2 with 192 cores and threads can outperform AMD’s EPYC Bergamo 9754 processor with 128 cores and 256 threads, both running at 360 W. In order to compete with the fastest x86 server processors, the Veyron V2 packs new type 1 and type 2 hypervisor extensions with nested virtualization, advanced interrupt architecture with interrupt virtualization, as well as external and self-host debug plus trace-to-memory.

Additionally, the V2 would be 40% faster than the V1 thanks to all the new RVA23 features that include UCIe chiplet interface, 512-bit vector unit + AI matrix extensions, server-class IOMMU, domain-specific acceleration and expanded RISC-V Software Ecosystem support.

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