DLCs for datacenters: Intel Software Defined Silicon in upcoming Xeon Sapphire Rapids locks CPU features behind a paywall
Late last year, Linux drivers for what appeared to be Intel's Software Defined Silicon (SDSi) feature were first discovered. These features are expected to make the cut later in Spring 2022 with the Linux 5.18 kernel. According to the notes, the new driver supports "post-manufacturing mechanism for activating additional silicon features".
The Register brought this to Intel's attention back then and received the following response,
We’re not going into a lot of details about Software Defined Silicon at this time. As you know, Intel regularly submits code to the Linux Kernel that could be used in future products. And that’s what happened in this case. If we plan to implement these updates in future products we will provide a deeper explanation of how they are implemented at that time."
Given that Intel plans to fully submit the commits to the 5.18 kernel this Spring, it is probably safe to assume that the upcoming 4th gen Sapphire Rapids Xeon CPUs would be the first to implement SDSi. The exact features that Intel would be licensing under SDSi are not yet known. There is currently no information on how this works either. However, according to Phoronix,
The SDSi kernel driver exposes a per-socket interface so their user-space application can provision an authentication key certificate that is written to internal NVRAM, provision their "capability activation payload", and reading of the SDSi state certificate that shows the CPU configuration state for a given processor."
That being said, based on the feature set we've seen with the 3rd gen Xeon Scalable SKUs, Intel may offer "DLCs" catering to various specialized use cases such as large (up to 4.5 TB) and medium (up to 2 TB) DDR support, optional AVX-512, networking virtualization, virtual machine densities, Intel Speed Select, etc.
In one way, this could be a cost-effective move since not all customers need to use every single feature of the processor. Intel also can manufacture lesser core/clock/TDP/instruction set variants and instead allow the user to manually unlock features as workflows scale. This also enables enterprises and datacenters to just buy capabilities as needed without having to reconfigure the whole server at the hardware level.
Intel's CPU paywall concept isn't exactly new, though. Back in 2010, the company first toyed with a DRM-esque idea called the Intel Upgrade Service that would "unlock" an extra 1 MB cache on the 2.8 GHz Pentium G6951 Clarkdale processor for a US$50 upgrade card that could be purchased on Best Buy.
Though met with severe criticism from the press, the company extended the program to the 2011 Sandy Bridge Core i3 SKUs. For instance, the Core i3-2312M with 2.1 GHz clock and 3 MB cache could be "upgraded" to the Core i3-2393M with 2.5 GHz clock and 4 MB cache. Though Intel tried its best to defend this approach back then, the Upgrade Service was discontinued in 2011 itself.
It remains to be seen whether a resurrection of this model will find success in the enterprise and datacenter segment.