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Computex 2024 | Intel Lunar Lake debuts as "most efficient" x86 design with combined 120 TOPS AI performance

Intel offers more insights into Lunar Lake SoCs. (Image Source: Intel)
Intel offers more insights into Lunar Lake SoCs. (Image Source: Intel)
Intel is offering deeper insights into the Lunar Lake architecture at Computex 2024. Lunar Lake will be a tiled 3D packaged design for laptops with a focus on per-per-Watt and AI performance. Lunar Lake marks the arrival of Lion Cove and Skymont cores, Xe2-LPG Battlemage iGPU, and a 47 TOPS NPU along with a host of other platform enhancements.

The battle for AI supremacy on the edge is just beginning to warm up. Intel, with its new Lunar Lake architecture, will be jostling for your hard-earned pie with Qualcomm Snapdragon X Elite / X Plus ARM SoCs, and AMD Strix Point Zen 5 Ryzen AI 300 Series APUs in what it claims to be most efficient x86 design yet.

Late last month, Intel threw a spanner in the Qualcomm's works by announcing the arrival of Lunar Lake CPUs for mobile with the promise of a combined 100 TOPS AI performance.

At Computex 2024, Intel is detailing some of the juicy stuff that goes into the innards of Lunar Lake. The company isn't announcing the exact SKUs or their individual configurations, but there's a lot in store and improvements from Meteor Lake seem to be pretty significant, at least on paper.

Lunar Lake: Platform overview

Lunar Lake continues to be based on Intel's Foveros 3D packaging technology that organizes various functioning units on the chip into tiles, primary ones being the Compute tile and the Platform Controller tile.

Lunar Lake is the first design that is outsourced to an external fab instead of being forged in Intel's own foundries. Intel still does not explicitly mention the fabrication node in its materials, but CEO Pat Gelsinger did indicate recently that the Lunar Lake CPU, GPU, and NPU are all being fabbed on TSMC N3B.

The use of a more compact Foveros 2.5D packaging means that less energy is needed is to move data off the die and into RAM. This enables Intel to directly integrate DRAM onto the package itself. According to Intel, Lunar Lake can offer up to 32 GB LPDDR5X-8500 dual-rank memory on die.

Compute tile

The Compute tile is comprised of the CPU clusters, Battlemage Xe2-LPG iGPU, and the 48 TOPS NPU. Lunar Lake uses a 4P+4E hybrid core design, which Intel claims is optimized for better single-threaded performance.

Each of the four Lion Cove P-cores gets 2.5 MB L2 cache along with a 12 MB shared L3 cache. The P-cores lack hyperthreading and Intel is confident that the available eight threads can take on 8C/16T offerings from AMD. The lack of hyperthreading likelys only pertain to Lunar Lake SKUs and not to the Lion Cove cores themselves.

The four Skymont E-cores, on the other hand, get 4 MB shared L2 cache. Skymont cores are particularly interesting this time given that leaks so far seem to suggest IPC equivalent to that of AMD Zen 3. Intel's own graph below indicates Skymont E-cores achieving up to 80% efficiency of the P-core at full Wattage.

Intel's Battlemage Arc GPU makes its debut on Lunar Lake in the form of Xe2-LPG much before a discrete version is available. Xe2-LPG brings with it eight Xe cores, eight RT cores, XMX (Xe Matrix eXtensions) AI Engine, and 8 MB of cache.

XMX is Intel's equivalent of Nvidia Tensor cores in GeForce RTX cards and are already a feature of desktop Alchemist Arc cards. Xe2-LPG brings XMX to the Arc iGPU for the first time, which should enable use of Intel XeSS super sampling tech at higher quality settings.

According to Intel, the Xe2-LPG iGPU on a Lunar Lake reference validation platform (RVP) is up to 50% faster than the Xe-LPG in Meteor Lake in 3DMark Time Spy. There is no mention of the exact configuration or specifications of the RVP, however.

XMX also helps in adding another 67 TOPS to the total AI performance. Together, the CPU, Xe2-LPG GPU, and the NPU can afford a total of 120 TOPS platform AI compute performance. Lunar Lake also brings forth a new media engine that support AV1 encode/decode and VVC/H.266 decode.

Power management

Lunar Lake also has a few tricks up its sleeve for improved power efficiency. Firstly, there is a memory side cache for low power consumption. Then there's a more capable low power island (LPI) that hopefully does a bit more than just keeping the device active in a low power state.

Intel is adding more power rails and informed telemetry to allow the SoC make better power decisions. Changes are also being made to Thread Director to improve efficiency with workload classification using machine learning.

Overall, Intel claims a 40% lower power requirement for the Lunar Lake RVP compared to Meteor Lake. This is during playback of YouTube 4K 30 AV1 video.

Platform Controller tile

The Platform Controller tile offers all the networking and I/O. Lunar Lake now integrates Wi-Fi 7 and Bluetooth 5.4 while offering 4x PCIe Gen 5 lanes and PCIe Gen 4 lanes along with 3x Thunderbolt 4.

There's also a new Partner Security Engine (PSE) in addition to the Silicon Security Engine (SSE), Graphics Security Controller (GSC), and Converged Security and Manageability Engine (CSME) that were already part of Meteor Lake.

Intel also said that the platform fabric is built for scalability with the ability to move IPs between tiles and nodes as needed.

Intel is pitching Lunar Lake as an efficiency champ and not necessarily as a performance powerhouse. Understandable, given the limelight ARM is stealing away from x86 and the manner in which it is turning out to be a viable platform to run full Windows.

Lunar Lake-powered laptops will launch some time in Q4 before which we should be getting a better idea of the SKUs on offer.

One thing is for sure, though. x86 on laptops cannot be written off just yet.


Intel Computex 2024 keynote

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> Expert Reviews and News on Laptops, Smartphones and Tech Innovations > News > News Archive > Newsarchive 2024 06 > Intel Lunar Lake debuts as "most efficient" x86 design with combined 120 TOPS AI performance
Vaidyanathan Subramaniam, 2024-06- 4 (Update: 2024-06- 4)