India is ready to test its own line of RISC-V desktop CPUs
The ongoing trade wars between the U.S. and China reintroduced the discussion regarding reciprocal PC hardware reliance. Many of the U.S.-based companies producing PC components manufacture their products in China, yet Chinese consumers do not benefit at all from such deals since the hardware still needs to be shipped to the U.S. and again back to China. Not to mention Trump raised the trade tariffs and China intends to do the same.
In order to circumvent this reliance cycle, China has been working on its own line of desktop CPUs for the past few years, and other countries are following suit. The European Union presented its first CPU designs in early June, and India also appears to be ready to test a wide range of RISC-V-based CPUs, as the Indian Institute of Technology Madras recently announced the availability of SDK toolkits for its Shakti processors.
Development for the Shakti CPUs started back in 2016, when certain researchers currently known as the RISE group at IIT planned to release RISC-V CPUs that would be competitive with commercially-available models from Intel, AMD and ARM. After three and a half years of development, the Shakti CPU family now includes different classes of processors, each designed with a specific market in mind. Here is a quick rundown for each class:
• C Class – 32-bit 5 stage in-order microcontroller class with 0.2 – 1 GHz clocks, aimed at mid-ranged application loads, low TDP and optional increased memory protection
• E Class – 3-stage in-order CPU for embedded applications such as IoT devices, robotic platforms etc.
• H Class – aimed at high-performance computing and analytics workloads, focused on single-thread performance, optional L4 cache memory, support for Gen-Z fabric and storage-class memory
• I Class – 64-bit out of-order CPU with 1.5 – 2.5 GHz clocks, focused on multi-threading applications for the mobile, storage and networking markets.
• M Class – CPU integrating up to eight I Class or C Class cores
• S Class – enhanced I Class version designed for workstation and server applications
• Experimental classes: T Class supports object-level security for micro-VM-like functionality and increased protection against buffer-overflow attacks; F Class includes even more security features and support for ECC memory