Interview | "Conversations around ARM vs. x86 power are false" Intel's Robert Hallock on Lunar Lake's strategy and how it is well-poised to challenge ARM's efficiency narrative

NBC: Lunar Lake (LNL) is said to offer 100 TOPS of total AI performance. What will be the power target this will be achieved at vis-à-vis Meteor Lake?

RH: Lunar Lake processors for laptops will significantly boost AI processing capabilities with up to 120 TOPS from CPU, GPU, and NPU (combined). This represents a threefold increase compared to our current Meteor Lake product(s). Assuming you are inquiring about product TDPs, specifications like this will be shared closer to launch.

However, we have disclosed that Lunar Lake’s package power consumption is generally reduced by 40% compared to Meteor Lake, so you can safely assume that Lunar Lake’s performance increases do not come at the cost of elevated TDP. The performance/watt is substantially improved for notebooks.

NBC: Apart from Skymont E-cores, does Lunar Lake also have standalone E-cores in a low power (LP) island as was the case with Meteor Lake? If so, are we looking at a 4+4+2 config?

RH: In the Meteor Lake product generation, our full configuration was: 2C2T LP E-cores, 8C8T E-cores, and 6C12T P-cores (total 16C22T). The LP E-core complex was generally pretty good at constraining workloads like video playback and teleconferencing but could not always achieve this goal because the thread counts sometimes exceeded the 2C2T size of the complex.

Looking at the 8C8T complex of E-cores, these were quite good at being efficient, but the new E-cores in Lunar Lake (“Skymont”) offer 1.68X more performance at the same frequency and can run at lower active power.

Because of the dramatic perf/W improvement in Skymont, we decided to merge the idea of E-cores and LP E-cores into one: Lunar Lake’s 4C4T E-core complex is also the low power island. Skymont cores give us a wider range of performance and power, which allows us to simplify the design while gaining ground in both power efficiency and compute performance.

We may not always make the same set of decisions in the future as core and process technologies change, but this is what made sense in the current generation, and we’re extremely pleased with the “dynamic range” of performance and power the Skymont complex can offer.

NBC: What is the rationale for not enabling hyperthreading on the P-cores with LNL? I understand P-cores are quite capable this time, but wouldn't it make sense to enable an HT option at least in the BIOS for laptops with higher power limits?

RH: At the time when Hyperthreading was introduced, it made for a clever solution to increasing performance without having to pack in more physical cores. But everyone in tech knows that an SMT thread does not necessarily offer the same performance as a “real” thread on a physical core.

We understand that this is a pretty radical conversation to be having, considering SMT has been a typical feature for nearly 20 years. But we’re entering an era where process technologies and core architectures can enable a new or different set of design decisions.

With Lunar Lake, we’ve actively decided to remove Hyperthreading because Skymont and Lion Cove (and their successors) allow us to achieve better performance, power, and area than SMT can provide. In other words: “real cores” are rapidly becoming a better solution than SMT threads.

This will not always be true of all products and all segments, but it’s the best answer for a product like Lunar Lake that is trying to maximize performance per watt in very low power scenarios.

This approach leads to a significant multi-dimensional improvement: by removing SMT, new P-cores provide 15% more performance per watt, 10% more performance per die area, and 30% more performance per power/area.

NBC: Will LNL PL1/PL2 values and TDP configurations be similar to what we see today with Meteor Lake (MTL), or can we expect them to be higher?

RH: We have not yet revealed those details but will be doing so at launch. Stay tuned!

NBC: Can we expect to see Thunderbolt 5 and Wi-Fi 7 becoming mainstream with LNL laptops?

RH: I imagine you will see some system designs that adopt a standalone Thunderbolt 5 controller, but Lunar Lake includes integrated Thunderbolt 4 and that will be the most common solution. Lunar Lake systems require a minimum of two Thunderbolt 4 ports, one on each side of the chassis, and up to three total ports are supported in the silicon.

Wi-Fi 7 is also integrated into the Lunar Lake SoC, offering significant advancements over Wi-Fi 6E. Wi-Fi 7's larger channels and advanced modulation techniques allow for theoretical maximum speeds up to 5.9 Gbps and improved reliability with ultra-low latency. The integration of the Digital MAC, logic, and memory into the SoC results in a smaller and more efficient design.

NBC: Are there any changes coming to the Intel Evo spec with LNL?

RH: Intel will provide specifics on the new Intel Evo edition at launch.

NBC: Can you explain why Intel has opted for TSMC N3B instead of an Intel in-house node like Intel 4?

RH: Intel opted for TSMC N3B for Lunar Lake as part of its IDM 2.0 strategy, allowing our design teams to choose process technologies that meet product schedule, power, and performance goals. The compute tile uses TSMC N3B, and the Platform Controller Tile uses TSMC N6, both connected to Intel's 1227.1 base tile via Intel’s Foveros technology.

Assembly, test, and packaging is also conducted in Intel facilities. Different products may drive a different set of process technology choices, but our IDM 2.0 strategy empowers us to make those choices rather than relying solely on process technology.

NBC: According to what we've been hearing so far, don't you think the naming scheme might be a might confusing for non-technical folks, especially since there seem to be no H, HX, or U labels anymore?

RH: While we have not yet disclosed model numbers for the Lunar Lake product, our direction and intent are uncomplicated. We will provide specifics on that prior to product availability.

NBC: Based on the above question, can we get to see H, HX, or U SKUs down the line or is it going to be all V?

RH: We will provide specifics on the SKU table at launch. 

NBC: Will Panther Lake offer support for backside power delivery or is it too early to discuss it yet?

RH: It's too early to discuss.

NBC: Finally, what are Intel's thoughts on the new wave of ARM laptops and are there any Intel's own ARM plans that you can discuss at the moment?

RH: It is our firm belief that the ongoing conversations around ARM vs. x86 power are based on a false premise because it is not the instruction set architecture (ISA) that broadly dictates power.

Our view is a physical one: transistors cost power. A CPU design that adds core counts, increases NPU size, increases graphics size, or adds fabric complexity is not free. These decisions intrinsically raise package power consumption and TDPs into the ballpark of what consumers historically see from conventional Windows/Linux processors.

In other words: implementing the features and performance the market expects has a “typical cost,” regardless of the x86 or ARM ISA. So, if adding complexity costs power on any ISA, then it becomes a battle between which set of design choices yields the best performance/power/area (PPA) to meet consumer expectations.

We believe Lunar Lake has the right set of design decisions to win:

• The Skymont E-core architecture raises IPC by 68%, allowing us to improve PPA by merging LP E-cores and E-cores into a single complex.
• The Lion Cove P-core architecture is +15 to +20% IPC. It’s also replanned and repartitioned to be more scalable and more precise in its voltage/clock selection.
• Thread Director once again improves with containment zones, which allow us to gracefully manage parasitic power cases into a low power position.
• We added an 8MB memory-side cache, which can obviate the need to access main memory-on-package. This reduces SoC power consumption on a regular basis.
• We moved memory on package, which reduces the PHY power cost of DRAM by ~40%. 
• Graphics perf/W improved by 1.5X.
• NPU performance improved by >2X at the same power, and ~4X overall.
• We built an entirely new low-power fabric to integrate the compute tile.
• We rebased our architectural strategy in this product around shedding the inefficiencies of SMT, which also allowed us to improve PPA

Because of choices like these, we believe that Lunar Lake can achieve lower package power than ARM designs ceteris paribus. We’re excited to show just how low power x86 can be in a time when ARM-on-Windows designs are going the other direction.

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