First Chinese CPU with proprietary instruction set launched by Loongson
A few months ago, Loongson was finalizing China’s first proprietary CPU instruction set dubbed LoongArch, and now the company is launching the first CPU models that include the new microcode. The Loongson 3A5000 processors integrate four cores with no hyperthreading technology, while the LoongArch microcode offers almost 2,000 instructions similar to existing mainstream architectures such as X86 and ARM, ensuring cross-instruction platform application compatibility.
Each of the four cores inside the Loongson 3A5000 CPU is running at 2.3 - 2.5 GHz and features a 64-bit superscalar GS464V autonomous microarchitecture with four fixed-point units, two 256-bit vector operation units and two access memory units. It also packs dual 64-bit DDR4-3200 controllers with ECC support and fout HyperTransport 3.0 controllers. To ensure lower power requirements, the processor comes with dynamic clock shutdown, dynamic clock frequency conversion and dynamic voltage regulation. Security is covered through a secure trusted module with Merchant Secret SM 2/3/4 hardware encryption. It looks like there will also be some mobile variants and availability will most likely be restricted to China.
As far as performance goes, the 3A5000 processors are 50% faster and 30% more energy efficient than the 3A4000 predecessor, and also maintain pin compatibility. 3A4000 was somewhere in line with AMD’s Excavator processors, so the new processors are probably matching the first gen Ryzen CPUs. Furthermore, the new chips get a single-core score of 26+ and a multi-core score of 80+ in SPEC CPU2006 through the GCC compiled environment.
Even though it is based on the new LoongArch microcode, the 3A5000 processor is still compatible with the older LoongISA architecture derived from the MIPS64 ISA. Loongson offers a Loongnix OS for client applications and a LoongOS for industrial control and terminal applications. Programs can be written through the existing GCC, LLVM and GoLang compilers, and compatibility with other mainstream microcodes is ensured through Java, JavaScript and NET virtual machines.
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