New MIT tech could lead to longer lasting devices and more capable AI systems

As demand for artificial intelligence and resource-intensive computing surges, something else is tagging along with it — energy demand. Traditional chip designs contribute to this waste by separating logic and memory components, forcing data to shuttle back and forth inefficiently. Now, a team of MIT researchers has come up with a solution that could significantly boost energy efficiency — stacking these components together on the back end of the chip.

This is different to what Intel does with Lunar Lake, and Apple with its M-series SoCs. Traditionally, sensitive transistors are built on one face of a silicon chip, while the other side is reserved for wiring. Adding more components is a tough job because the heat required to do so would destroy the existing layer. Now an MIT team — led by Yanjie Shao — has tackled this problem by developing a low-temperature fabrication process.

Using a unique material called amorphous indium oxide, the team grew ultra-thin transistor layers at just 150 °C (302 °F) — cool enough to protect the circuits underneath. This allowed them to stack active transistors directly onto the back end, effectively merging logic and memory into a single, compact vertical stack.

Now, we can build a platform of versatile electronics on the back end of a chip that enable us to achieve high energy efficiency and many different functionalities in very small devices. We have a good device architecture and material to work with, but we need to keep innovating to uncover the ultimate performance limits. — Yanjie Shao.

Improving on the existing design, the researchers used a ferroelectric material called hafnium-zirconium-oxide to create 20-nanometer transistors. In tests, the devices demonstrated lightning-fast switching speeds of just 10 nanoseconds, which is the limit of the team's measuring equipment, all while consuming significantly less voltage than comparable technology.