Apple Silicon and Nuvia veterans reveal unusual CPU core that keeps its ISA options open

Nuvacore is a relatively new CPU startup founded by veteran engineers with backgrounds at Apple, Nuvia and Qualcomm, and it is now beginning to reveal how it plans to build its first general-purpose processor core codenamed WarpCore. Gerard Williams III, John Bruno, and Ram Srinivasan founded the company, all of whom have deep experience in custom CPU design. Williams previously co-founded Nuvia before Qualcomm acquired the company. Subsequently, Nuvacore has also brought in David Williamson, a former Apple CPU engineering leader, as Senior Vice President of Hardware Engineering.

The company is now starting to explain what makes WarpCore different. In an X post published on September 29, the company introduced what it calls a "Core First" development model. Instead of choosing an instruction set architecture at the start of the project, Nuvacore says it can build much of the foundational CPU core IP first and select the ISA later, depending on the system it or one of its partners ultimately wants to build.

That is a notable deviation from conventional CPU design methodology, where the target ISA typically shapes the design from the outset. Nuvacore says decoupling parts of the microarchitecture from the instruction set gives its engineers additional freedom to focus first on performance, power efficiency and silicon area. The company has not yet said which ISA WarpCore will ultimately use. However, its hiring material references RISC-V, Arm64 and x86 as architectures relevant to its engineering work, suggesting that the underlying design is being developed with substantial ISA flexibility in mind.

Of course, it does not mean an instruction set can simply be bolted onto the core at the end. Decode, privilege levels, memory ordering, exception handling and software compatibility still place major constraints on CPU design. With Nuvacore, enough of the performance-critical machinery can apparently be developed before the final ISA choice is locked down.

The company's job listings offer a few clues about what that foundational work includes. It is hiring engineers across branch prediction, instruction scheduling, register renaming, out-of-order execution, load/store design, cache and memory subsystems, coherence and performance modelling. It is also recruiting for RTL, verification and physical design roles, including work extending through tape-out and post-silicon correlation.

The legal side of the eventual ISA choice remains unresolved as well. RISC-V is comparatively straightforward because it does not require an Arm-style architecture licence. An Arm implementation based on Nuvacore's own microarchitecture would require the appropriate Arm architecture rights somewhere along the way, and given Arm is in the business of selling CPU design IP, getting one could get tricky, more so with Arm's legal tiff with Qualcomm/Nuvia in the past. Lastly, x86 presents an even higher barrier because implementation rights are tightly controlled.

That raises another possibility: WarpCore may be intended as reusable CPU IP that partners with the relevant architectural licences can adapt. The company itself has not yet clarified whether its long-term model will centre on complete CPUs, licensable core IP, semi-custom silicon, or some combination of the three.

For now, critical details such as WarpCore's process node, cache hierarchy, pipeline configuration, vector capabilities or tape-out schedule have not been revealed, but the fact that it is deliberately keeping the ISA decision open makes this one of the more unusual clean-sheet CPU projects currently in development.