Intel, Cadence strengthen collaboration to accelerate SoC design on cutting-edge 18A process nodes and beyond

In accordance with information provided by Intel's recent press release, Intel Foundry Services (IFS) and Cadence Design Systems Inc. have announced a multiyear strategic agreement to jointly develop customized intellectual property (IP) and optimization techniques for Intel's 18A process technology. This technology incorporates RibbonFET gate-all-around transistors and PowerVia backside power delivery.

The collaboration aims to streamline system-on-chip (SoC) projects, focusing on Intel 18A process technology and beyond. By integrating advanced transistor and power delivery technologies, the partnership seeks to enhance performance, power efficiency, and overall chip design. Targeting market segments such as artificial intelligence/machine learning, high-performance computing, and premium mobile computing, the collaboration aims at addressing the demand for advanced IP standards to maximize the benefits of advanced packaging and silicon process technologies.

According to Stuart Pann, Intel's senior vice president and general manager of Intel Foundry Services (IFS), the expanded partnership with Cadence is expected to bolster the IP ecosystem for IFS' customers. Pann highlighted the potential for leveraging Cadence's design solutions to facilitate the development of high-volume, high-performance, and power-efficient SoCs on Intel's process technologies.

Cadence's portfolio includes advanced memory protocols, PCI Express, and UCI Express, which are expected to enable scalable, high-performance designs. These designs are anticipated to expedite time to market and leverage IFS' advanced silicon technologies and 3D-IC packaging capabilities.

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