Leaked slides confirm Tiger Lake-U Gen12 Xe's 2x graphics boost over Ice Lake, a new FIVR implementation, and HW-accelerated 12-bit HEVC/VP9 encode-decode

Last week, we exclusively reported that Tiger Lake-U's Gen12 Xe graphics would be nearly 2x faster than the Gen11 iGPU in Ice Lake-U. We have also reported earlier that Gen12 Xe would natively support 12-bit HEVC VP9 codecs. Recently, leaker @momomo_us has managed to discover a few slides that confirm these findings. 

According to these slides, Tiger Lake would be available in a 4+2 configuration with four CPU cores and two Gen12 Xe cores in Y and U parts. Tiger Lake-Y will have a nominal TDP of 9 W with 5 W cTDP down and 15 W cTDP up whereas Tiger Lake-U will have a nominal TDP on 28 W with 15 W and 10 W cTDP down. 

Apart from HEVC and VP9, Gen12 Xe will also support native AV1 decode, which includes 10-bit 4:2:0 16K stills and 8-bit 4:2:0 4K and 2K video. 8K60 HEVC with 4:2:0, 4:2:2, and 4:4:4 chroma subsampling modes are also supported. 

The Tiger Lake platform will also support Intel Harrison Peak 2 WLAN, which is hardware ready for Bluetooth 5.1. Intel is also changing the power deliver architecture from Comet Lake-U by using several fully integrated voltage regulators (FIVRs). FIVRs were first introduced with Haswell and offer a way of integrating the VRs on the processor itself instead of taking up space on the motherboard. With Tiger Lake-U, Intel is moving several power gates such as VCCPLL_OC, VCCMPHY, V3.3A_PCH to the SoC. The slide also says Tiger Lake would support LP DDR5 with VDD2 voltages of 1.10 V for LPDDR4x and 1.05V for LPDDR5.

All in all, Tiger Lake-U looks to be quite the architectural improvement that may brighten up Intel's prospects again. However, all we know so far is the purported graphics performance gains over Ryzen 4000 Renoir. AMD will still likely have the lead when it comes to pure CPU performance.